Symbolic Supervisory Control of Timed Discrete Event Systems

With the increasing complexity of computer systems, it is crucial to have efficient design of correct and well-functioning hardware and software systems. To this end, it is often desired to control the behavior of systems to possess some desired properties. A specific class of systems is called discrete event systems (DES). DES deal with `discrete' quantities, e.g., ``number of robots in a manufacturing cell'', and their processes are driven by instantaneous `events', e.g., ``start of a machine''. In this thesis, the focus is on DES and an extension of such systems, which also considers the time points at which the events may occur, called \emph{timed DES (TDES)}. Real-time applications such as communication networks, manufacturing facilities, or the execution of a computer program, can be considered into TDES. Having a DES or TDES, with some given specifications, by utilizing a well-known mathematical framework, called supervisory control theory (SCT), it is possible to automatically generate a supervisor that restricts the system's behavior towards the specifications, only when it is necessary. Applying the SCT to large and complex systems, typically follows with some issues, concerning computational complexity and modeling aspects, which is tackled in this thesis. We model DES by extended finite automata (EFAs), state transition models that contain discrete-valued variables. TDES are modeled by an augmentation of EFAs, called timed EFAs (TEFAs), which contain a set of discrete-valued clocks. Based on EFAs or TEFAs, the supervisor can be symbolically computed, using binary decision diagrams (BDDs), data structures that could, in many cases, lead to smaller representation of the state space. For complex systems, the computed supervisor may consist of many states, causing representation and implementation difficulties. To tackle this, based on the states of the supervisor, we symbolically compute logical constraints that will be attached to the original models to restrict the system's behavior. Consequently, we present a framework, where given a set of EFAs or TEFAs, the supervisor is computed using BDDs, and represented in a modular manner based on the computed logical constraints. The framework has been developed, implemented, and applied to industrial case studies

Modeling sequential resource allocation systems using Extended Finite Automata

Deadlock avoidance for resource allocation systems (RAS) is a well-established problem in the Discrete Event System (DES) literature. This paper is mainly concerned with modeling the class of Conjunctive / Disjunctive sequential resource allocation systems (C/D RAS) as finite automata extended with variables. The proposed modeling approach allows for modeling multiple instance execution, routing flexibility and failure handling. With an appropriate model of the system, a symbolic approach is then used to synthesize the optimal supervisor, in the least restrictive sense. Furthermore, a set of compact logical formulae can be extracted and attached to the original model, which results in a modular and comprehensible representation of the supervisor

BDD-based supervisory control on extended finite automata

In this paper, we settle some problems that are encountered when modeling and synthesizing complex industrial systems by the supervisory control theory. First, modeling such huge systems with explicit state-transition models typically results in an intractable model. An alternative modeling approach is to use extended finite automata (EFAs), which is an augmentation of ordinary automata with variables. The main advantage of utilizing EFAs for modeling is that more compact models are obtained. The second problem concerns the ease to understand and implement the supervisor. To handle this problem, we represent the supervisor in a modular manner by extending the original EFAs by compact conditional expressions generated from the monolithic supervisor. In order to, potentially, be able to handle complex systems efficiently, the models are symbolically represented by binary decision diagrams (BDDs). All computations that are performed in this framework are based on BDD operations. The framework has been implemented in a supervisory control tool and applied to industrially relevant benchmark problems

Automatic Generation of Controllers for Collision-Free Flexible Manufacturing Systems

A method for automatic generation of non-blocking controllers that generate collision-free flexible manufacturing cells is presented in this paper. Today, industry demands on flexible production sometimes require significant changes in location, orientation and configuration of industrial robots and other moving devices, when new products are introduced. All these changes pose a threat to the devices to collide while sharing workspace. To avoid this, a formal model of the operations in a manufacturing system is generated, and for each operation state a corresponding 3D simulation shape is created. A collision-free system is then achieved by considering pairs of colliding shapes as forbidden states. The automatic generation also includes a synthesis procedure, where a non-blocking and controllable supervisor is generated based on guard generation. The guards are computed by binary decision diagrams, which means that complex systems can be handled, still generating comprehensible restrictions that are easily included in PLC-code

Efficient Symbolic Supervisory Synthesis and Guard Generation: Evaluating partitioning techniques for the state-space exploration

The supervisory control theory (SCT) is a model-based framework, which automatically synthesizes a supervisor that restricts a plant to be controlled based on specifications to be fulfilled. Two main problems, typically encountered in industrial applications, prevent SCT from having a major breakthrough. First, the supervisor which is synthesized automatically from the given plant and specification models might be incomprehensible to the users. To tackle this problem, an approach was recently presented to extract compact propositional formulae (guards) from the supervisor, represented symbolically by binary decision diagrams (BDD). These guards are then attached to the original models, which results in a modular and comprehensible representation of the supervisor. However, this approach, which computes the supervisor symbolically in the conjunctive way, might lead to another problem: the state-space explosion, because of the large number of intermediate BDD nodes during computation. To alleviate this problem, we introduce in this paper an alternative approach that is based on the disjunctive partitioning technique, including a set of selection heuristics. Then this approach is adapted to the guard generation procedure. Finally, the efficiency of the presented approach is demonstrated on a set of benchmark examples

Symbolic Computation of Nonblocking Control Function for Timed Discrete Event Systems

In this paper, we symbolically compute a minimally restrictive nonblocking supervisor for timed discrete event systems, in the supervisory control theory context. The method is based on Timed Extended Finite Automata, which is an augmentation of extended finite automata (EFAs) by incorporating discrete time into the model. EFAs are ordinary automaton extended with discrete variables, guard expressions and action functions. To tackle large problems all computations are based on binary decision diagrams (BDDs). The main feature of this approach is that the BDD-based fixed-point computations is not based on “tick” models that have been commonly used in this area, leading to better performance in many cases. As a case study, we effectively computed the minimally restrictive nonblocking supervisor for a well-known production cell

Supplement for the paper entitled “A BDD-Based Approach for Designing Maximally Permissive Deadlock Avoidance Policies for Complex Resource Allocation Systems”

This electronic document provides some supportive material to the paper entitled “A BDD-Based Approach for Designing Maximally Permissive Deadlock Avoidance Policies for Complex Resource Allocation Systems” that has been submitted to IEEE Transactions on Automation Science and Engineering (T-ASE)

Evaluating Optimization Solvers and Robust Semantics for Simulation-Based Falsification

Temporal-logic based falsification of Cyber-Physical Systems is a testing technique used to verify certain behaviours in simulation models, however the problem statement typically requires some model-specific tuning of parameters to achieve optimal results. In this experience report, we investigate how different optimization solvers and objective functions affect the falsification outcome for a benchmark set of models and specifications. With data from the four different solvers and three different objective functions for the falsification problem, we see that choice of solver and objective function depends both on the model and the specification that are to be falsified. We also note that using a robust semantics of Signal Temporal Logic typically increases falsification performance compared to using Boolean semantics

Reduced-order synthesis of operation sequences

In flexible manufacturing systems a large number of operations need to be coordinated and supervised to avoid blocking and deadlock situations. The synthesis of such supervisors soon becomes unmanageable for industrial manufacturing systems, due to state space explosion. In this paper we therefore develop some reduction principles for a recently presented model based on self-contained operations and sequences of operations. First sequential operation behaviors are identified and related operation models are simplified into one model. Then local transitions without interaction with other operation models are removed. This reduction principle is applied to a synthesis of non-blocking operation sequences, where collisions among moving devices are guaranteed to be avoided by a flexible booking process. The number of states in the synthesis procedure and the computation time is reduced dramatically by the suggested reduction principle

Industrial Temporal Logic Specifications for Falsification of Cyber-Physical Systems

In this benchmark proposal, we present a set of large specifications stated in Signal Temporal Logic (STL) intended for use in falsification of Cyber-Physical Systems. The main purpose of the benchmark is for tools that monitor STL specifications to be able to test their performance on complex specifications that have structure similar to industrial specifications. The benchmark itself is a Git repository which will therefore be updated over time, and new specifications can be added. At the time of submission, the repository contains a total of seven Simulink requirement models, resulting in 17 generated STL specifications